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1 ?2000 integrated device technology, inc. august 2001 dsc-3729/04 pin description features u u u u u 32k x 32 memory configuration u u u u u supports high performance system speed: commercial and industrial: 11 11ns clock-to-data access (50mhz) 12 12ns clock-to-data access (50mhz) u u u u u lbo input selects interleaved or linear burst mode u u u u u self-timed write cycle with global write control ( gw ), byte write enable ( bwe ), and byte writes ( bw x) u u u u u power down controlled by zz input u u u u u single 3.3v power supply (+10/-5%) u u u u u packaged in a jedec standard 100-pin rectangular plastic thin quad flatpack (tqfp). description the idt71v433 is a 3.3v high-speed 1,048,576-bit sram orga- nized as 32k x 32 with full support of various processor interfaces including the pentium? and powerpc?. the flow-through burst archi- tecture provides cost-effective 2-1-1-1 performance for processors up to 50 mhz. 32k x 32 3.3v synchronous sram flow-through outputs idt71v433 a 0 Ca 14 address inputs input synchronous ce chip enable input synchronous cs 0 , cs 1 chips selects input synchronous oe output enable input asynchronous gw global write enable input synchronous bwe byte write enable input synchronous bw 1 C bw 4 individual byte write selects input synchronous clk clock input input n/a adv burst address advance input synchronous adsc address status (cache controller) input synchronous adsp address status (processor) input synchronous lbo linear / interleaved burst order input dc zz sleep mode input asynchronous i/o 0 Ci/o 31 data input/output i/o synchronous v dd , v ddq core and i/o power supply (3.3v) power n/a v ss , v ssq array ground, i/o ground power n/a 3729 tbl 01 pentium is a trademark of intel corp. powerpc is a trademark of international business machines, inc. the idt71v433 sram contains write, data-input, address and control registers. there are no registers in the data output path (flow- through architecture). internal logic allows the sram to generate a self-timed write based upon a decision which can be left until the extreme end of the write cycle. the burst mode feature offers the highest level of performance to the system designer, as the idt71v433 can provide four cycles of data for a single address presented to the sram. an internal burst address counter accepts the first cycle address from the processor, initiating the access sequence. the first cycle of output data will flow-through from the array after a clock-to-data access time delay from the rising clock edge of the same cycle. if burst mode operation is selected ( adv =low), the subsequent three cycles of output data will be available to the user on the next three rising clock edges. the order of these three addresses will be defined by the internal burst counter and the lbo input pin. the idt71v433 sram utilizes idt's high-performance 3.3v cmos process, and is packaged in a jedec standard 14mm x 20mm 100-pin thin plastic quad flatpack (tqfp).
2 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges pin definitions (1) symbol pin function i/o active description a 0 Ca 14 address inputs i n/a synchronous address inputs. the address register is triggered by a combination of the rising edge of clk and adsc low or adsp low and ce low. adsc address status (cache controller) i low synchronous address status from cache controller. adsc is an active low input that is used to load the address registers with new addresses . adsc is not gated by ce . adsp address status (processor) i low synchronous address status from processor. adsp is an active low input that is used to load the address registers with new addresses. adsp is gated by ce . adv burst address advance i low sync hrono us ad dres s adv ance . adv is an ac tive low input that is used to advance the internal burst counter, controlling burst access after the initial address is loaded. when this input is high the burst counter is not incremented; that is, there is no address advance. bwe byte write enable i low synchronous byte write enable gates the byte write inputs bw 1 C bw 4 . if bwe is low at the rising edge of clk then bw x inputs are passed to the next stage in the circuit. a byte write can still be blocked if adsp is low at the rising edge of clk. if adsp is high and bw x is low at the rising edge of clk then data will be written to the sram. if bwe is high then the byte write inputs are blocked and only gw can initiate a write cycle. bw 1 C bw 4 individual byte write enables i low synchronous byte write enables. bw 1 controls i/o(7:0), bw 2 controls i/o(15:8), etc. any active byte write causes all outputs to be disabled. adsp low disables all byte writes. bw 1 C bw 4 must meet specified setup and hold times with respect to clk. ce chip enable i low synchronous chip enable. ce is used with cs 0 and cs 1 to enable the idt71v433. ce also gates adsp . clk clock i n/a this is the clock input. all timing references for the device are made with respect to this input. cs 0 chip select 0 i high synchronous active high chip select. cs 0 is used with ce and cs 1 to enable the chip. cs 1 chip select 1 i low synchronous active low chip select. cs 1 is used with ce and cs 0 to enable the chip. gw global write enable i low synchronous global write enable. this input will write all four 8-bit data bytes when low on the rising edge of clk. gw supercedes individual byte write enables. i/o 0 Ci/o 31 data input/output i/o n/a synchronous data input/output (i/o) pins. only the data input path is registered and triggered by the rising edge of clk. outputs are flow-through. lbo linear burst i low when lbo is high the interleaved order (intel) burst sequence is selected. when lbo is low the linear (powerpc) burst sequence is selected. lbo has an internal pull-up resistor. oe output enable i low as ync hronous output e nable . whe n oe is high the i/o pins are in a high- impedence state. when oe is low the data output drivers are enabled if the chip is also selected. v dd power supply n/a n/a 3.3v core power supply inputs. v ddq power supply n/a n/a 3.3v i/o power supply inputs. v ss ground n/a n/a core ground pins. v ssq ground n/a n/a i/o ground pins. nc no connect n/a n/a nc pins are not electrically connected to the chip. zz sleep mode i high asynchronous sleep mode input. zz high will gate the clk internally and power do wn the idt71v433 to its lowe st power consumpti on lev el. data re tention is guaranteed in sleep mode. zz has an internal pull-down resistor. 3729 tbl 02 note: 1. all synchronous inputs must meet specified setup and hold times with respect to clk.
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 3 functional block diagram a 0 Ca 14 address register clr a 1 * a 0 * 15 2 15 a 2 Ca 14 32k x 32 bit memory array internal address a 0 ,a 1 bw 4 bw 3 bw 2 bw 1 byte 1 write register 32 32 adsp adv clk adsc cs 0 cs 1 byte 1 write driver byte 2 write driver byte 3 write driver byte 4 write driver byte 2 write register byte 3 write register byte 4 write register 8 8 8 8 gw ce bwe lbo i/o 0 Ci/o 31 oe data input register 32 output buffer powerdown zz d q enable register oe burst sequence ce clk en clk en q1 q0 2 burst logic binary counter 3729 drw 01 .
4 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges absolute maximum dc ratings (1) capacitance (t a = +25c, f = 1.0mhz, tqfp package) notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v dd , v ddq and input terminals only. 3. i/o terminals. symbol rating value unit v term (2 ) terminal voltage with respect to gnd C0.5 to +4.6 v v term (3 ) terminal voltage with respect to gnd C0.5 to v dd +0.5 v t a operating temperature 0 to +70 o c t bias temperature under bias C55 to +125 o c t stg storage temperature C55 to +125 o c p t power dissipation 1.2 w i out dc output current 50 ma 3729 tbl 05 note: 1. this parameter is guaranteed by device characterization, but not production tested. symbol parameter (1 ) conditions max. unit c in input capacitance v in = 3dv 4 pf c i/ o i/o capacitance v out = 3dv 8 pf 3729 tbl 06 recommended dc operating conditions notes: 1. v ih and v il as indicated is for both input and i/o pins. 2. v ih (max) = 6.0v for pulse width less than t cyc /2, once per cycle. 3. v il (min) = C1.0v for pulse width less than t cyc /2, once per cycle. symbol parameter min. typ. max. unit v dd core supply voltage 3.135 3.3 3.63 v v ddq i/o supply voltage 3.135 3.3 3.63 v v ss, v ssq ground 0 0 0 v v ih input high voltage 2.0 (1 ) ____ v ddq +0.3 (2 ) v v il input low voltage C0.5 (3 ) ____ 0.8 v 3729 tbl 04 grade temperature v ss v dd v ddq commercial 0 c to +70 c 0v 3.3v+10/-5% 3.3v+10/-5% industrial C40c to +85c 0v 3.3v+10/-5% 3.3v+10/-5% 3729 tbl 03 recommended operating temperature and supply voltage
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 5 100 99 98 97 96 95 94 93 92 91 90 87 86 85 84 83 82 81 89 88 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 a 6 a 7 c e c s 0 b w 4 b w 3 b w 2 b w 1 c s 1 v d d v s s c l k g w b w e o e a d s c a d s p a d v a 8 a 9 nc 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 n c n c n c n c n c lb o a 14 a 13 a 12 a 11 a 10 v d d v s s a 0 a 1 a 2 a 3 a 4 a 5 i/o 31 i/o 30 v ddq v ssq i/o 29 i/o 28 i/o 27 i/o 26 v ssq v ddq i/o 25 i/o 24 v ss v dd i/o 23 i/o 22 v ddq v ssq i/o 21 i/o 20 i/o 19 i/o 18 v ssq v ddq i/o 17 i/o 16 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 i/o 14 v ddq v ssq i/o 13 i/o 12 i/o 11 i/o 10 v ssq v ddq i/o 9 i/o 8 v ss nc v dd zz (2) i/o 7 i/o 6 v ddq v ssq i/o 5 i/o 4 i/o 3 i/o 2 v ssq v ddq i/o 1 i/o 0 pk100-1 3729 drw 02 v ss (1) i/o 15 nc nc nc nc n c . pin configuration top view tqfp notes 1. pin 14 does not have to be directly connected to v ss as long as the input voltage is v il . 2. pin 64 can be left unconnected and the device will always remain in active mode.
6 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges synchronous truth table (1, 2) notes: 1. l = v il , h = v ih , x = dont care. 2. zz = low for this table. 3. oe is an asynchronous input. operation address used ce cs 0 cs 1 adsp adsc adv gw bwe bw x oe (3 ) clk i/o deselected cycle, power down none h x x x l x x x x x - hi-z deselected cycle, power down none l x h l x x x x x x - hi-z deselected cycle, power down none l l x l x x x x x x - hi-z deselected cycle, power down none l x h x l x x x x x - hi-z deselected cycle, power down none l l x x l x x x x x - hi-z read cycle, begin burst external l h l l x x x x x l - d out read cycle, begin burst externallhllxxxxxh - hi-z read cycle, begin burst external l h l h l x h h x l - d out read cycle, begin burst external l h l h l x h l h l - d out read cycle, begin burst external l h l h l x h l h h - hi-z write cycle, begin burst external l h l h l x h l l x - d in write cycle, begin burst external l h l h l x l x x x - d in read cycle, continue burst next x x x h h l h h x l - d out read cycle, continue burst next x x x h h l h h x h - hi-z read cycle, continue burst next x x x h h l h x h l - d out read cycle, continue burst next x x x h h l h x h h - hi-z read cycle, continue burst next h x x x h l h h x l - d out read cycle, continue burst next h x x x h l h h x h - hi-z read cycle, continue burst next h x x x h l h x h l - d out read cycle, continue burst next h x x x h l h x h h - hi-z write cycle, continue burst next x x x h h l h l l x - d in write cycle, continue burst next x x x h h l l x x x - d in write cycle, continue burst next h x x x h l h l l x - d in write cycle, continue burst next h x x x h l l x x x - d in read cycle, suspend burst current x x x h h h h h x l - d out read cycle, suspend burst current x x x h h h h h x h - hi-z read cycle, suspend burst current x x x h h h h x h l - d out read cycle, suspend burst current x x x h h h h x h h - hi-z read cycle, suspend burst current h x x x h h h h x l - d out read cycle, suspend burst current h x x x h h h h x h - hi-z read cycle, suspend burst current h x x x h h h x h l - d out read cycle, suspend burst current h x x x h h h x h h - hi-z write cycle, suspend burst currentxxxhhhhl lx - d in write cycle, suspend burst current x x x h h h l x x x - d in write cycle, suspend burst currenthxxxhhhl lx - d in write cycle, suspend burst current h x x x h h l x x x - d in 3729 tbl 07
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 7 linear burst sequence table ( lbo =v ss ) interleaved burst sequence table ( lbo =v dd ) asynchronous truth table (1) synchronous write function truth table (1) notes: 1. l = v il , h = v ih , x = dont care. 2. multiple bytes may be selected during the same cycle. operation gw bwe bw 1 bw 2 bw 3 bw 4 read h h x x x x read h l h h h h write all bytes l x x x x x write all bytes h l l l l l write byte 1 (2 ) hl l h h h write byte 2 (2 ) hl h l h h write byte 3 (2 ) hl h h l h write byte 4 (2 ) hl h h h l 3729 tbl 08 notes: 1. l = v il , h = v ih , x = dont care. 2. synchronous function pins must be biased appropriately to satisfy operation requirements. operation oe zz i/o status power read l l data out (i/o 0 Ci/o 31 )active read h l high-z active write x l high-z data in (i/o 0 Ci/o 31 )active deselected x l high-z standby sleep mode x h high-z sleep 3729 tbl 09 note: 1. upon completion of the burst sequence the counter wraps around to its initial state. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 0 0 1 1 1 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11 10 0 1 00 3729 tbl 10 note: 1. upon completion of the burst sequence the counter wraps around to its initial state. sequence 1 sequence 2 sequence 3 sequence 4 a1 a0 a1 a0 a1 a0 a1 a0 first address 0 0 0 1 1 0 1 1 second address 0 1 1 0 1 1 0 0 third address 1 0 1 1 0 0 0 1 fourth address (1 ) 11 00 0 1 10 3729 tbl 11
8 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (v dd = 3.3v +10/-5%, commercial and industrial temperature ranges) figure 3. lumped capacitive load, typical derating figure 2. high-impedence test load (for t ohz , t chz , t olz , and t dc1) dc electrical characteristics over the operating temperature and supply voltage range (1) (v hd = v ddq ?0.2v , v ld = 0.2v) 351 w +3.3v 317 w 5pf* 3729 drw 04 data out 1 2 3 4 20 30 50 100 200 d t cd (typical, ns) capacitance (pf) 80 5 6 3729 drw 05 note: 1. the lbo pin will be internally pulled to v dd if it is not actively driven in the application and the zz pin will be internally pulled to v ss if not actively driven. symbol parameter test conditions min. max. unit |i l i | input leakage current v dd = max., v in = 0v to v dd ___ 5a |i li | zz & lbo input leakage current (1 ) v dd = max., v in = 0v to v dd ___ 30 a |i lo | output leakage current ce > v ih or oe > v ih , v out = 0v to v dd , v dd = max. ___ 5a v ol output low voltage i ol = 5ma, v dd = min. ___ 0.4 v v oh output high voltage i oh = C5ma, v dd = min. 2.4 ___ v 3729 tbl 12 notes: 1. all values are maximum guaranteed values. 2. at f = f max, inputs are cycling at the maximum frequency of read cycles of 1/t cyc while adsc = low; f=0 means no input lines are changing. idt71v433s11 idt71v433s12 symbol parameter test conditions com'l. ind. com'l. ind. unit i dd operating core power supply current device selected, outputs open, v dd = max., v ddq = max., v in > v ih or < v il , f = f max (2 ) 220 220 210 210 ma i sb standby core power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v ih or < v il , f = f max (2 ) 45 45 40 40 ma i sb1 full standby core power supply current device deselected, outputs open, v dd = max., v ddq = max., v in > v hd or < v ld , f = 0 (2 ) 15 15 15 15 ma i zz full sleep mode core power supply current zz > v hd , v dd = max. 15 15 15 15 ma 3729 t bl 13 * including scope and jig capacitance. ac test conditions ac test loads figure 1. ac test load 50 w data out z 0 =50 w 3729 drw 03 v ddq /2 input pulse levels input rise/fall times input timing reference levels output timing reference levels ac test load 0 to 3.0v 2ns 1.5v 1.5v see figures 1 and 2 3729 tbl 14
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 9 symbol parameter 71v433s11 71v433s12 unit min. max. min. max. clock parameters t cyc clock cycle time 20 ____ 20 ____ ns t ch (1 ) clock high pulse width 6 ____ 6 ____ ns t cl (1 ) clock low pulse width 6 ____ 6 ____ ns output parameters t cd clock high to valid data ____ 11 ____ 12 ns t cdc clock high to data change 3 ____ 3 ____ ns t clz (2 ) clock high to output active 0 ____ 0 ____ ns t chz (2 ) clock high to data high-z 3 6 3 6 ns t oe output enable access time ____ 4 ____ 4ns t olz (2 ) output enable low to data active 0 ____ 0 ____ ns t ohz (2 ) output enable high to data high-z ____ 6 ____ 6ns setup times t sa address setup time 2.5 ____ 2.5 ____ ns t ss address status setup time 2.5 ____ 2.5 ____ ns t sd data in setup time 2.5 ____ 2.5 ____ ns t sw write setup time 2.5 ____ 2.5 ____ ns t sav address advance setup time 2.5 ____ 2.5 ____ ns t sc chip enable/select setup time 2.5 ____ 2.5 ____ ns hold times t ha address hold time 0.5 ____ 0.5 ____ ns t hs address status hold time 0.5 ____ 0.5 ____ ns t hd data in hold time 0.5 ____ 0.5 ____ ns t hw write hold time 0.5 ____ 0.5 ____ ns t hav address advance hold time 0.5 ____ 0.5 ____ ns t hc chip enable/select hold time 0.5 ____ 0.5 ____ ns sleep mode and configuration parameters t zzpw zz pulse width 100 ____ 100 ____ ns t zz r (3 ) zz recovery time 100 ____ 100 ____ ns t cfg (4 ) configuration set-up time 80 ____ 80 ____ ns 3729 tbl 15 ac electrical characteristics (v dd = 3.3v +10/-5%, commercial and industrial temperature ranges) notes: 1. measured as high above 2.0v and low below 0.8v. 2. transition is measured 200mv from steady-state. 3. device must be deselected when powered-up from sleep mode. 4. t cfg is the minimum time required to configure the device based on the lbo input. lbo is a static input and must not change during normal operation.
10 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges notes: 1. o1 (ax) represents the first output from the external address ax. o1 (ay) represents the first output from the external addre ss ay; o2 (ay) represents the next output data in the burst sequence of the base address ay, etc., where a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. 2. zz input is low and lbo is dont care for this cycle. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. timing waveform of read cycle (1,2) t c h z t s a t s c t h s g w , b w e , b w x t s w t c l t s a v t h w t h a v c lk a d s p a d s c (1) a d d r e s s t c y c t c h t h a t h c t o e t o h z o e t c d t o l z o 1(a x) d a t a o u t t c d c o 1(a y) o 2 (a y) o 2(a y) a d v a d v inserts a w ait-state c e , c s 1 (n ote 3 ) 372 9 drw 06 f low -through r ead b urst f low -through r ead o utput d isabled a x a y t s s o 1(a y) o 4(a y) o 3(a y) (b urst w raps around to its initial state) .
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 11 timing waveform of combined read and write cycles (1,2,3) notes: 1. device is selected through entire cycle; ce and cs 1 are low, cs 0 is high. 2. zz input is low and lbo is don't care for this cycle. 3. o1 (ax) represents the first output from the external address ax. i1 (ay) represents the first input from the external addres s ay. o1 (az) represents the first output from the external address az; o2 (az) represents the next output data in the burst sequence of the base address az, etc., where a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. o 1(a z) c lk a d s p a d d r e s s g w a d v o e d a t a o u t t c y c t c h t c l t h a t s w t h w t c lz a x a y a z i1(a y) t s d t h d t o lz t c d t c d c d a t a in (2) t o e o 1(a z) 3729 drw 07 s ingle r ead f low -through b urst r ead w rite t o h z t s s t s a o 3(a z) o 2(a z) o 4(a z) o 1(a x) . t h s
12 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges timing waveform of write cycle no. 1 ? gw controlled (1,2,3) notes: 1. zz input is low, bwe is high, and lbo is dont care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input fro m the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc., where a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2(ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. 3729 drw 08 a d d r e s s c lk a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y a z a d v d a ta o u t o e t h c t s d i1(a x) i1(a z) i2(a y) th d t o h z d a ta in t h a v o 4(a w ) c e , c s 1 g w t s w (n ote 3) i2(a z) i3(a z) i4(a y) i3(a y) i2(a y) t s a v ( a d v suspends burst) i1(a y) b w e is ignored w hen a d s p initiates burs t t s c (1) (3) o 3(a w ) . t h w
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 13 timing waveform of write cycle no. 2 ? byte controlled (1,2,3) notes: 1. zz input is low, gw is high, and lbo is dont care for this cycle. 2. o4 (aw) represents the final output data in the burst sequence of the base address aw. i1 (ax) represents the first input fro m the external address ax. i1 (ay) represents the first input from the external address ay; i2 (ay) represents the next input data in the burst sequence of the base address ay, etc., where a 0 and a 1 are advancing for the four word burst in the sequence defined by the state of the lbo input. in the case of input i2(ay) this data is valid for two cycles because adv is high and has suspended the burst. 3. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. a d d r e s s c lk a d s p a d s c t c y c t s s t h s t c h t c l t h a t s a a x a y b w x a d v d a t a o u t o e t h c t s d s ingle w rite b urst w rite i1(a x) i2(a y) i2(a y) ( a d v su spend s b urst) i2(a z) th d r ead b urst e xtended b urst w rite t o h z d a t a in t s a v t s w o 4(a w ) c e , c s 1 b w e t s w (n o te 3) i1(a z) a z i4(a y) i1(a y) 37 29 drw 09 i4(a y) i3(a y) t s c b w e is ig nore d w hen a d s p initia tes burs t b w x is igno red w h en a d s p in itiates bu rs t i3(a z) o 3(a w ) . t h w t h w
14 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges timing waveform of sleep (zz) and power-down modes (1,2,3) notes: 1. device must power up in deselected mode. 2. lbo input is dont care for this cycle. 3. it is not necessary to retain the state of the input registers throughout the power-down cycle. 4. cs 0 timing transitions are identical but inverted to the ce and cs 1 signals. for example, when ce and cs 1 are low on this waveform, cs 0 is high. t c y c t s s t c l t c h t h a t s a t s c t h c t o e t o lz t h s c lk a d s p a d s c a d d r e s s g w c e , c s 1 a d v d a t a o u t o e z z s ingle r ead s nooze m ode t z z p w 37 29 d rw 10 o 1(a x) a x (n ote 4) t z z r a z .
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 15 non-burst read cycle timing waveform notes: 1 zz input is low, adv is high, and lbo is dont care for this cycle. 2. (ax) represents the data for address ax, etc. 3. for read cycles, adsp and adsc function identically and are therefore interchangeable. clk adsp gw , bwe , bw x ce , cs 1 cs 0 address adsc data out oe av aw ax ay az 3729 drw 11 (av) (aw) (ax) (ay) .
16 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges non-burst write cycle timing waveform notes: 1. zz input is low, adv and oe are high, and lbo is don't care for this cycle. 2. (ax) represents the data for address ax, etc. 3. although only gw writes are shown, the functionality of bwe and bw x together is the same as gw . 4. for write cycles, adsp and adsc have different limitations. clk adsp gw ce , cs 1 cs 0 address adsc data in av aw ax az ay (av) (aw) (ax) (az) (ay) 3729 drw 12 .
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 17 100-pin thin quad flatpack (tqfp) package diagram outline
18 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges ordering information plastic thin quad flatpack, 100 pin (pk100-1) s power x speed pf package pf idt 71v433 11 12 t cd in nanoseconds 3729 drw 13 device type part number speed in megahertz t cd parameter clock cycle time 50 mhz 50 mhz 11 ns 12 ns 20 ns 20 ns . x process/ temperature range blank i commercial (0 cto+70 c) industrial (C40 cto+85 c) 71v433s11pf 71v433s12pf
6.42 idt71v433 32k x 32, 3.3v synchronous sram with flow-through outputs commercial and industrial temperature ranges 19 corporate headquarters for sales: for tech support: 2975 stender way 800 345-7015 or 408 727-6116 sramhelp@idt.com santa clara, ca 95054 fax: 408 492-8674 800 544-7726, x4033 www.idt.com the idt logo is a registered trademark of integrated device technology, inc. datasheet document history 09/10/99 updated to new format pg. 1, 8, 9, 17 revised speed offerings to 11 and 12 ns at 50 mhz pg. 3C5 adjusted page layout, added extra page pg. 5 added notes to pin configuration ` pg. 11C14 updated notes pg. 18 added datasheet document history 10/08/99 pg. 1, 4, 8, 9, 17 added industrial temperature range offerings 04/04/00 pg. 17 added 100pintqfp package diagram outline 08/09/00 not recommended for new designs 08/17/01 removed not recommended for new designs from the background on the datasheet

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